1. Field of the Invention
Embodiments of the present invention generally relate to dynamic random access memory (DRAM) devices and, more particularly, to internal circuits of DRAM devices that generate self-refresh signals.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices store data in memory elements that have an associated retention time. DRAM devices are referred to as dynamic because if the memory elements are not refreshed (e.g., accessed) within the retention time, the data stored in the memory element may be lost. During normal operating conditions, a memory controller connected to a DRAM device typically generates periodic signals to refresh the memory elements in order to retain the data. However, for special operating conditions, such as a low power mode, the memory controller may be shut down and unable to generate the period refresh signals. Typically, to maintain data in such special operating conditions, DRAM devices may be placed in a self-refresh mode, in which the memory elements are refreshed by signals generated by an internal self-refresh circuit.
The self-refresh circuit generally includes a timing circuit and address decoding logic configured to access all memory elements at least once within the retention time. The timing circuit typically includes a programmable counter driven by an oscillator to generate a self-refresh timing signal to initiate a self-refresh sequence in which a memory element selected by the address decoding logic is accessed. The address decoding logic may select a different memory element for each access. Due to variations in materials and manufacturing processes, the oscillator frequency may vary which may, in turn, result in variations in the frequency of the self-refresh signal. If these variations are great enough, the frequency of the self-refresh signal may be insufficient to ensure each memory element is accessed within the retention time, and data may be lost.
Therefore, to account for variations in the oscillator frequency, the self-refresh circuit is typically calibrated (or trimmed) during the manufacturing process. Because the frequency of the self-refresh signal is generally equal to the oscillator frequency multiplied by a pre-programmed count loaded into the programmable counter, variations in the oscillator frequency may be compensated for by varying the pre-programmed count accordingly. Conventionally, to adjust this time during the manufacturing process, a DRAM device is placed into a special test mode in which the frequency of the self-refresh signal may be measured externally by a testing device (e.g., the self-refresh signal may be driven onto an output pin during the special test mode).
Generally, the testing device determines an optimal value for the pre-programmed count based on the measured frequency of the self-refresh signal. The optimal value is calculated to ensure that the frequency of the self-refresh signal is sufficient to ensure each memory element will be addressed within the retention time. Once calculated, the optimal value is permanently stored in non-volatile storage elements, such as fuses, on the DRAM device. After this initial calibration (e.g., on future power-up sequences), the DRAM device may then load the pre-programmed count from the non-volatile storage. Because the oscillator frequency for each DRAM device may vary independently, the self-refresh frequency for each DRAM is typically measured and trimmed individually. Therefore, self-refresh calibration tends to add considerable time to a DRAM manufacturing process, which may limit manufacturing throughput.
Accordingly, what is needed is an improved method and apparatus for self-refresh calibration of DRAM devices that results in reduced calibration time and increased manufacturing throughput.
Embodiments of the present invention generally provide methods, apparatus, and systems for trimming a periodic self-refresh timing signal of a dynamic random access memory (DRAM) device.
For one embodiment, a method for internally trimming a periodic self-refresh timing signal of a dynamic random access memory (DRAM) device generated by a programmable counter driven by an oscillator generally includes receiving a reference timing signal supplied from a device external to the DRAM device and internally determining a trim value for programming the programmable counter based on the reference timing signal.
For one embodiment, a method for internally trimming a periodic self-refresh timing signal of a dynamic random access memory (DRAM) device generated by a programmable counter driven by an oscillator generally includes receiving a reference timing signal supplied from a device external to the DRAM device and internally determining a trim value for programming the programmable counter by comparing a period of the reference timing signal to a period of the self-refresh timing signal.
For one embodiment, a dynamic random access memory (DRAM) device generally includes a self-refresh circuit having a programmable counter driven by an oscillator for generating a periodic self-refresh timing signal and a self-trim circuit configured to receive a reference timing signal supplied by a device external to the DRAM device and to generate a trim value for programming the programmable counter based on a period of the reference timing signal.
For one embodiment, a dynamic random access memory (DRAM) device generally includes a self-refresh circuit having a programmable counter driven by an oscillator for generating a periodic self-refresh timing signal and a self-trim circuit configured to measure a period of a reference timing signal supplied by a device external to the DRAM device and to generate a trim value for programming the programmable counter based on the measured period.
For one embodiment, a system for calibrating dynamic random access memory (DRAM) devices generally includes a testing device configured to generate a periodic reference timing signal and one or more DRAM devices coupled to the testing device via a bus, each having a self-refresh circuit with a programmable counter driven by an oscillator for generating a periodic self-refresh timing signal and a self-trim circuit configured to receive a reference timing signal supplied by a device external to the DRAM device and to generate a trim value for programming the programmable counter based on a period of the reference timing signal.